BUS index's lane — a bus master's slot in that SAME array (one-summing-bus §"The build"
step 2), which is where its EQ, gate, comp, delay and reverb run.
The MASTER lane's index — MAIN's slot in the same lane array the input strips live in.
Publish the lane's stage RUN ORDER — the reorderable built-ins as native stage ids (deriveStageOrder). The native side normalises (dedupe, bounds, the always-present-EQ guarantee) and publishes torn-free; a stage the list omits simply does not run.
Drive the lane's DRIVE stage — the saturator, with its own local oversampling.
Drive the lane's GATE KEY — what its detector listens to, filtered, and the listen latch.
Arm / rack / drop strip index's insert point point — the send/return port pair a
hosted plugin chain hangs off. false for a lane/point the node does not carry.
The native strip DSP surface the built-in-processor bridge drives (setStripEq/setStripDyn), as a structural subset so it is unit-testable with a fake.